I got curious, so:
arm-none-eabi-gcc --version
arm-none-eabi-gcc (15:12.2.rel1-1) 12.2.1 20221205
allocate_oids count=3
config_stepper oid=0 step_pin=PG0 dir_pin=PG1 invert_step=-1 step_pulse_ticks=0
config_stepper oid=1 step_pin=PF13 dir_pin=PF12 invert_step=-1 step_pulse_ticks=0
config_stepper oid=2 step_pin=PC13 dir_pin=PF0 invert_step=-1 step_pulse_ticks=0
finalize_config crc=0
...
ECHO Test result is: {"%.0fK" % (3. * freq / ticks / 1000.)}
I got 44
and 185
ticks respectively for STM32H7 (slightly faster than currently in docs).
Master: 1 stepper 9091K
and 3 steppers 6452K
I did overclock to 435Mhz, to still account for TMC optimization, and fixed several small things in the code to make timers works.
Patched: 1 stepper 9886K
and 3 steppers 7054K
, ticks count are same.
So, ~8%.
(much less changes than I expected)
Patched branch: GitHub - nefelim4ag/klipper at stm32h7-overclock
I think it may be better to compute “MAX_TIME” based on the MCU clock, but that is more like overkill.
Right now I changed 5 → 4.5 because of 2000_000_000 / 435_000_000 = 4.59
prehistory: a buddy of mine runs servos with really high microstepping because of some servo controller limitation (like 80000 per rotation). Servo controllers use pulses instead of edges for stepping, so it is easily got Stepper too far in past
So, for reference, with “normal” stepper drivers (pulse limit is 44 ticks ~ 100ns) the limit is:
- 171 ticks or 2339K (400Mhz) → 2544K (435Mhz)
- 361 ticks or 2216K → 2410K
- 535 ticks or 2242K → 2439K
So, I think there is a slightly different dependency between edge
and pulse mode in performace.