STM32G0 USB clock config

leptun · October 15, 2022, 7:36am

Hi!

I noticed something weird in the clock_setup() for stm32g0. At the end, the USB is switched to use PLLQ as the clock source. This makes sense since earlier the PLL is configured to output 48MHz on PLLQ. What doesn’t make sense is the actual line of code. The code sets USBSEL to 2, but according to the datasheet, that results in configuring the USB to use HSE as input, not PLLQ. The comment also says that it works in practice, but I really doubt that it works unless HSE is a 48MHz crystal. Am I understanding this wrong or is this a bug? I unfortunately don’t have a stm32g0bx board at the moment to test if it works or not (and of course it’s unavailable everywhere right now).

Alan · October 22, 2022, 8:10am

github.com

STMicroelectronics/STM32CubeG0/blob/master/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h#L437


      
          #endif /* FDCAN1 || FDCAN2 */
          
          
#if defined(RCC_CCIPR2_USBSEL)
          /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
            * @{
            */
          #if defined(RCC_HSI48_SUPPORT)
          #define RCC_USBCLKSOURCE_HSI48         0x00000000U            /*!< HSI48 oscillator clock selected as USB clock */
          #endif /* RCC_HSI48_SUPPORT */
          #define RCC_USBCLKSOURCE_HSE           RCC_CCIPR2_USBSEL_0  /*!< HSE oscillator clock selected as USB clock */
          #define RCC_USBCLKSOURCE_PLL           RCC_CCIPR2_USBSEL_1  /*!< PLL "Q" selected as USB clock */
          /**
            * @}
            */
          #endif /* RCC_CCIPR2_USBSEL */
          
          
/** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source
            * @{
            */
          
          
#define RCC_ADCCLKSOURCE_SYSCLK       0x00000000U             /*!< SYSCLK used as ADC clock */

github.com

STMicroelectronics/STM32CubeG0/blob/master/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h#L6910


      
          #define RCC_CCIPR2_I2S2SEL_1              (0x2UL << RCC_CCIPR2_I2S2SEL_Pos)     /*!< 0x00000008 */
          #define RCC_CCIPR2_FDCANSEL_Pos           (8U)
          #define RCC_CCIPR2_FDCANSEL_Msk           (0x3UL << RCC_CCIPR2_FDCANSEL_Pos)    /*!< 0x00000300 */
          #define RCC_CCIPR2_FDCANSEL               RCC_CCIPR2_FDCANSEL_Msk
          #define RCC_CCIPR2_FDCANSEL_0             (0x1UL << RCC_CCIPR2_FDCANSEL_Pos)    /*!< 0x00000100 */
          #define RCC_CCIPR2_FDCANSEL_1             (0x2UL << RCC_CCIPR2_FDCANSEL_Pos)    /*!< 0x00000200 */
          #define RCC_CCIPR2_USBSEL_Pos             (12U)
          #define RCC_CCIPR2_USBSEL_Msk             (0x3UL << RCC_CCIPR2_USBSEL_Pos)     /*!< 0x00003000 */
          #define RCC_CCIPR2_USBSEL                 RCC_CCIPR2_USBSEL_Msk
          #define RCC_CCIPR2_USBSEL_0               (0x1UL << RCC_CCIPR2_USBSEL_Pos)      /*!< 0x00001000 */
          #define RCC_CCIPR2_USBSEL_1               (0x2UL << RCC_CCIPR2_USBSEL_Pos)      /*!< 0x00002000 */
          /********************  Bit definition for RCC_BDCR register  ******************/
          #define RCC_BDCR_LSEON_Pos               (0U)
          #define RCC_BDCR_LSEON_Msk               (0x1UL << RCC_BDCR_LSEON_Pos)          /*!< 0x00000001 */
          #define RCC_BDCR_LSEON                   RCC_BDCR_LSEON_Msk
          #define RCC_BDCR_LSERDY_Pos              (1U)
          #define RCC_BDCR_LSERDY_Msk              (0x1UL << RCC_BDCR_LSERDY_Pos)         /*!< 0x00000002 */
          #define RCC_BDCR_LSERDY                  RCC_BDCR_LSERDY_Msk
          #define RCC_BDCR_LSEBYP_Pos              (2U)
          #define RCC_BDCR_LSEBYP_Msk              (0x1UL << RCC_BDCR_LSEBYP_Pos)         /*!< 0x00000004 */
          #define RCC_BDCR_LSEBYP                  RCC_BDCR_LSEBYP_Msk

According to the header file provided by STMicroelectronics, the corresponding value of PLLQ is 2.
In addition, USB can be used normally when it is 2, and USB cannot recognize when it is 1.

So I guess the manual is wrong? Verifying with STMicroelectronics FAE

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STM32G0 USB clock config

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